The breakdown characteristics of parallel-plane (semi-infinite) junctions typically provide an upper bound on the breakdown characteristics of power semiconductor devices. This is because the breakdown voltages of practical power devices having finite length P-N junctions are typically limited by the occurrence of high electric fields either within interior portions of the devices or at the edges of the devices.
Although many specific edge termination techniques have been proposed in the literature to improve breakdown voltage, these techniques can generally be classified into two basic types, namely, planar terminations based upon masked diffusion processes and beveled terminations based upon the selective removal of material from the vicinity of the edge junctions. In both these techniques, floating field plates and floating field rings have been found to be useful in enhancing the breakdown voltage of power semiconductor devices. Such conventional techniques are more fully described in Section 3.6 of a textbook by B. J. Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (1995), pp. 81-113.
Typical power semiconductor devices include the insulated gate bipolar transistor (IGBT) and static-induction transistor (SIT). FIG. 1 illustrates a schematic cross-sectional view of a conventional insulated gate bipolar transistor containing an N+ buffer region 13 on a P+ substrate 12 having an anode electrode 11 on a face thereof. An N- drift region 14 is also provided on the buffer region 13. Adjacent P-type base regions 15 are also provided in the drift region 14 by implanting and then diffusing P-type dopants into an upper surface of the drift region 14 using an insulated gate electrode, comprising an insulating layer 18 and gate electrode 19, as an implant mask. N-type source regions 16 are also provided in the P-type base regions 15. Contact to the base and source regions is provided by a cathode contact 17 on the upper surface of the drift region 14. As will be understood by those skilled in the art, the P-type substrate 12, the N-type buffer and drift regions 13-14, and P-type base region 15 collectively form the emitter, base and collector of a vertical P-N-P bipolar transistor having a floating base. In order to turn the vertical P-N-P bipolar transistor on, the anode electrode 11 is biased positive relative to the cathode electrode 17 and a positive bias is applied to the gate electrode 19. The application of a positive bias to the gate electrode 19 causes the formation of inversion-layer channels in the base regions 15. These inversion-layer channels electrically connect the source regions 16 to the drift region 14 and provide the base drive current needed to initiate turn-on of the P-N-P transistor.
FIG. 2 illustrates a schematic cross-sectional view of a static induction transistor comprising a drain electrode 21, P+ substrate region 22, N+ buffer region 23, N- drift region 24, P+ gate regions 25, N+ source region 26 and source electrode 27. The source electrode 27 may be electrically isolated from the gate regions 25 by an electrically insulating region 28. As will be understood by those skilled in the art, forward conduction can be controlled by controlling the magnitude of the reverse bias appearing across the P-N junctions formed between the gate regions 25 and drift region 24. When this reverse bias is substantial, the depletion regions formed in the drift region 24 merge to pinch-off the conductive channel formed in the space between the gate regions 25 and thereby prevent forward conduction. Thus, the resistance of the channel region can be modulated by the magnitude of the reverse bias appearing across the gate region/drift region junctions.
Unfortunately, both of the above described power semiconductor devices are susceptible to premature breakdown because the base regions 15 of FIG. 1 and gate regions 25 of FIG. 2 do not form semi-infinite parallel-plane P-N junctions with the drift regions 14 and 24, respectively. This premature breakdown is caused by electric field crowding at the curved edges of the base and gate regions. Moreover, the degree of field crowding is worse when the junction depths are small compared to the depletion layer thickness in the drift region.
As described above, in order to enhance the breakdown voltages of power semiconductor devices, several types of structures have been developed. Two well known structures can be made by a simplified fabrication method. One of these structures is a floating field ring 48 which is spaced apart from a main junction region 46 in a substrate region 44, as illustrated by FIG. 3. An insulating region 49 may also be provided on a face of the substrate. The other of these structures is a field plate 58 which is connected to a main junction 56 at the face of a substrate 54 and is spaced from the face by an electrically insulating region 59, as illustrated by FIG. 4. Referring again to FIG. 3, a depletion layer 45 indicated by a dotted line may be generated and extended from the main junction region 46 to an outer edge of the floating field ring 48 when the main junction region is reverse biased. This prevents electric field crowding in the region "W.sub.S " which designates the spacing between the main junction region 46 and the floating field ring 48. As a result, the device of FIG. 3 may be able to support a breakdown voltage in a range of about 60-80% of the ideal breakdown voltage of a parallel-plane junction. Referring again to FIG. 4, a depletion layer 55 indicated by a dotted line may be generated in the substrate 54 because of the presence of the field plate 58. As a result, the device of FIG. 4 may be able to support a breakdown voltage in a range of about 60% of the ideal breakdown voltage of a parallel-plane junction. To enhance the breakdown voltage of the structure of FIG. 4, an insulating layer 59 (e.g., SiO.sub.2) may be provided, as illustrated. As will be understood by those skilled in the art, if the insulating layer 59 is thick, breakdown will typically occur in region "A", however if the insulating layer 59 is thin then breakdown will typically occur in region "B".
Notwithstanding these above described attempts to increase the breakdown voltage ratings of power semiconductor devices to the near ideal levels associated with parallel-plane junctions, there still continues to be need for structures which can improve the breakdown voltage ratings of power devices even further.